1. Field
Embodiments of the present invention relate to an apparatus and a method for offset cancellation in duty cycle corrections.
2. Related Art
Electronic devices are ubiquitous. Many of these devices rely on internal clocks to synchronize and trigger transmission of data to coordinate the actions of circuits within the electronic devices. These devices may further utilize communication data links with a half-rate clock, that is, these devices may have a double data rate (e.g., circuits using the clock signal for synchronization may become active at both the rising and the falling edges of the clock cycle.).
However, in electronic devices that utilize double data rate systems, duty cycle error may occur. Duty cycle error occurs when a duty cycle of a clock signal within a period deviates from an ideal clock period (e.g., an ideal clock period having 50% duty cycle where the clock is a high signal for 50% of the period and a low signal for 50% of the period). This duty cycle error may consequently reduce timing margins of double data rate systems, and may cause degradation of performance.
Consequently, duty cycle correction circuits have been developed to mitigate clock duty cycle error. However, duty cycle correction circuits may introduce an additional intrinsic offset that is indistinguishable from actual duty cycle error. Accordingly, the offset produced by the duty cycle correction circuits hinder achievable duty cycle correction.